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Xilinx ISE〔 100728 xilinx.com〕 (Integrated Synthesis Environment)〔(Handbook of Networked and Embedded Control Systems ), Springer Science & Business Media, 14-Nov-2007〕 is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Xilinx ISE is a design environment for FPGA products from Xilinx, and is tightly-coupled to the architecture of such chips, and cannot be used with FPGA products from other vendors.〔 The Xilinx ISE is primarily used for circuit synthesis and design, while ISIM or the ModelSim logic simulator is used for system-level testing.〔(Circuit Design with VHDL ), MIT Press, 2004〕〔(Advances in Computer Science and Information Engineering ), Springer Science & Business Media, 11-May-2012〕 Other components shipped with the Xilinx ISE include the Embedded Development Kit (EDK), a Software Development Kit (SDK) and ChipScope Pro.〔(Embedded Systems Design with Platform FPGAs ), Morgan Kaufmann, 10-Sep-2010〕 Since 2012, Xilinx ISE has been discontinued in favor of Vivado Design Suite, that serves the same roles as ISE with additional features for system on a chip development.〔(Vivado Design Suite ), First version released in 2012, Xilinx Downloads〕 Xilinx released the last version of ISE in October 2013 (version 14.7), and states that "ISE has moved into the sustaining phase of its product life cycle, and there are no more planned ISE releases".〔(ISE 14.7 Updates ), Xilinx Downloads〕 ==User Interface== The primary user interface of the ISE is the Project Navigator, which includes the design hierarchy (Sources), a source code editor (Workplace), an output console (Transcript), and a processes tree (Processes).〔〔(FPGA Prototyping By Verilog Examples ), John Wiley & Sons, 20-Sep-2011〕 The Design hierarchy consists of design files (modules), whose dependencies are interpreted by the ISE and displayed as a tree structure.〔 For single-chip designs there may be one main module, with other modules included by the main module, similar to the main() subroutine in C++ programs.〔 Design constraints are specified in modules, which include pin configuration and mapping.〔The Processes hierarchy describes the operations that the ISE will perform on the currently active module.〔 The hierarchy includes compilation functions, their dependency functions, and other utilities.〔 The window also denotes issues or errors that arise with each function.〔 The Transcript window provides status of currently running operations, and informs engineers on design issues.〔 Such issues may be filtered to show Warnings, Errors, or both.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Xilinx ISE」の詳細全文を読む スポンサード リンク
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